Integrated circuits have progressed to advanced technologies with smaller feature sizes, such as 16 nm, 9 nm and 7 nm. In these advanced technologies, the devices (such as transistors) shrink and therefore induce various issues, such as contact to gate bridging concern. Furthermore, three dimensional transistors with fin active regions are often desired for enhanced device performance. Those three dimensional field effect transistors (FETs) formed on fin active regions are also referred to as FinFETs. FinFETs are desired to have narrow fin width for short channel control, which leads to smaller S/D regions than those of planar FETs. This will further degrade the contact to S/D landing margin. Along with the scaling down of the device sizes, the contact size was continuously shrunk for high-density gate pitch requirement. To shrink the contact size without impacting contact resistance, there are challenges including material integration, processing and designing constrains. Other concerns include line-end shortening and line-end to line-end bridging, leading to either contact-to-fin active connection opening or contact-to-contact leakage (bridging). To reduce the line end shortening, it requires a wider space rule or more aggressive reshaping by optical proximity correction (OPC) on the line end, which will impact the cell size or cause bridging in a given cell pitch. This is getting even worse on fin transistors because fin active regions are very narrow. Especially, in the logic circuits or memory circuits, some local interconnection features are desired to have better interconnection without losing the circuit density. Therefore, there is a need for a structure and method for fin transistors and contact structure to address these concerns for enhanced circuit performance and reliability.